module portareg
	(clock, resetn, init, load, INIT, DATA, Q);
input			clock, resetn;
input			init, load;
input	[11:0]	INIT;
input	[11:0]	DATA;
output	[11:0]	Q;

reg		[11:0]	Q;

always @(posedge clock or negedge resetn)
begin
	if (!resetn) Q <= 12'b0;
	else if (init) Q <= INIT;
	else if (load) Q <= DATA[11:0];
end
endmodule